1. Field of the Invention
This invention relates to semiconductor circuits. More particularly, it relates to circuitry used to access data in a memory device.
2. Background of Related Art
The basic principle of Double Data Rate (DDR) Synchronous Dynamic Random Access Memory (SDRAM), or DDR-SDRAM, is very simple. DDR-SDRAM is RAM that transfers data on both 0-1 and 1-0 clock transitions, theoretically yielding twice the data transfer rate of normal SDRAM. Thus, while a DDR-SDRAM memory module is clocked at the same speed as normal SDRAM, it is able to transport double the amount of data by using the rising as well as falling edge of the clock signal for data transfers.
During any data access, a controller provides the DDR SDRAM with a clock, inverted clock, address, and control signals. During a write cycle, the controller also provides data as well as a data strobe signal (DQS). During a read cycle, the DDR-SDRAM provides data and the DQS signal. Accordingly, the DQS signal is bi-directional because it is used to clock data into the DDR-SDRAM during a write cycle, and the other direction into the controller during a read cycle. Bank pre-charging, refreshes, and so forth are handled in a DDR-SDRAM controller in much the same way they are handled in a standard SDRAM.
The DDR-SDRAM specification requires that the clock and inverted clock received from the controller cross within a very tight window. The crossing point of these clocks is considered the clock edge in the DDR SDRAM specification.
To maximize setup and hold time windows, the controller must drive DQS 90° out of phase with the data. Data is clocked by the DDR SDRAM on both edges of DQS. During a read, the DDR SDRAM provides both data and DQS. However, the DDR SDRAM provides data and DQS coincident with each other. This means the controller must either provide the 90° phase shift internally or find another way to clock in data. In addition, DQS is a strobed signal. It is driven while there is a transaction in progress, but tri-stated otherwise.
To achieve the ideal 90° phase shift, one of the most difficult issues addressed in the design of a Double Data Rate (DDR) SDRAM controller is delaying the SDRAM data strobe (DQS) to the center of the read window.
In conventional Double Data Rate (DDR) SDRAM controllers, it is common design practice to use Delay Locked Loops (DLLs) to implement a fixed, predetermined delay of the SDRAM read data strobe (DQS) to the approximate center of the received data eye. However, this use of DLLs providing a fixed amount of DQS delay is seen by the inventors of the present invention to have particular disadvantages. In particular, this delay is usually based on a calculated optimal value, which may not, in practice, be the optimal value.
At the Double Data Rate (DDR) SDRAM side, all data and data strobes (DQS) are clocked out by the same clock signal provided by the DDR SDRAM controller, and all will transit at nominally the same time. To capture the data from the DDR, the controller must delay the received DQS strobes so that the strobe transition occurs as close as possible to the center of the received data window, or “eye”.
To design a robust data capture circuit, several factors are taken into account including, e.g., DDR timing parameters, as well as board level and package skews. Typically, a DDR SDRAM controller is implemented in an FPGA or ASIC, in which case internal routing mismatches and PVT (Process, Voltage, and Temperature) for the controller device must also be considered. This is all well documented in literature available from DDR manufacturers such as the “DesignLine”, Vol. 8, Issue 3, 3Q99, available from MICRON™. The final result of this analysis results in a fixed DQS delay value (DLYDQS) which a DLL is used to implement.
FIG. 3 shows an exemplary conventional DDR read data capture circuit using a DLL circuit to implement a fixed DQS delay.
In particular, the conventional DDR read data capture circuit shown in FIG. 3 uses n+1 identical programmable delay lines 302a–302d, 310. The master “Programmable Delay 1” 302a through “Programmable Delay n” 302d are used to implement the programmable delay portion of a delay locked loop (DLL) 300. When the DLL 300 reaches lock, the total delay through these n delay lines 302a–302d is equal to one (1) clock period (tCLK) of the clock signal CLK. Since all the programmable delays 302a–302d, 310 are identical, the delay through each individual programmable delay element 302a–302d, 310 is equal to the clock period divided by n (tCLK/n). To delay DQS to the pre-calculated center of the data eye, the value of n is conventionally chosen such that tCLK/n=DLYDQS. A slave programmable delay line 310 is then used to implement the delay of DQS. Since the slave programmable delay line 310 is identical to the master programmable delay lines 302a–302d, DQS will be delayed by tCLK/n.
One of the disadvantages of such a conventional SDRAM controller is that it relies on dividing a clock period by a value, n, to obtain a desired delay. Since n must be an integer value, and the clock is usually the clock provided to the DDR SDRAMs, it is realized by the inventors of the present application that the resulting delay value will probably not be exactly equal to the actual, optimal delay value.
There is a need for better techniques and designs for centering DQS data strobes based on actual, optimal values.